| Produced | 1981 |
|---|---|
| Common manufacturer(s) |
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| Max. CPU clock rate | 5 MHz to 8 MHz |
The Intel iAPX 432 was a commercially unsuccessful 32-bit microprocessor architecture, introduced in 1981.
The project was Intel's first 32-bit microprocessor design, and intended to be the company's main product line for the 1980s. Many advanced multitasking and memory management features were implemented in hardware, leading to the design being referred to as a Micromainframe. ("iAPX" reportedly stands for intel Advanced Processor architecture, the X coming from the Greek letter Chi.)
Originally designed for clock frequencies of up to 10 MHz, actual devices sold were specified for maximum clock speeds of 4 MHz, 5 MHz, 7 MHz and 8 MHz respectively[1] with a peak performance of 2 million instructions per second at 8 MHz.[2]
Direct hardware support for various data structures was intended to allow modern operating systems for the iAPX 432 to be implemented using far less program code than for ordinary processors; combined with direct support for object-oriented programming and garbage collection, this made the hardware (mostly the microcode part) much more complex than most processors of the era, especially microprocessors.
Early systems built around the iAPX 432 were rather slow and expensive, one of the reasons being that Intel's engineers were unable to translate this large design into a very efficient first implementation using the semiconductor technology of the day. A lack of optimization in a rather premature Ada compiler developed for the processor was another major factor, perhaps more important than the processor implementation itself. In 1982, typical benchmark tests ran at roughly 1/4 the speed of the new and fast 80286 chip at the same clock frequency. This initial performance gap was probably the main reason why Intel's plan to replace the 8086-line (later known as the x86 architecture) with the iAPX 432 failed.
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The 432 project started in 1975 as the 8800, so named as a follow-on to the existing 8008 and 8080 CPUs. The design was intended to be purely 32-bit from the outset, and be the backbone of Intel's processor offerings in the 1980s. As such, it was to be considerably more powerful and complex than their existing "simple" offerings. However, the design was well beyond the capabilities of the existing process technology of the era, and had to be split into several individual chips.
The core of the design—the main processor—was termed the General Data Processor (GDP) and built as two chips: one (the 43201) to fetch and decode instructions, the other (the 43202) to execute them. Most systems would also include a third chip: the 43203 Interface Processor (IP) which operated as a channel controller for I/O.
These were some of the largest IC designs of the era. The two-chip GDP had a combined count of approximately 97,000 transistors while the single chip IP had approximately 49,000. By comparison, the Motorola 68000 (introduced in 1979) had approximately 40,000 transistors.
In 1983, Intel released two additional integrated circuits for the iAPX 432 Interconnect Architecture: the 43204 Bus Interface Unit (BIU) and 43205 Memory Control Unit (MCU). These chips allowed for nearly glueless multiprocessor systems with up to 63 nodes.
Several design features of the iAPX 432 conspired to make it a little slower at the hardware level than many contemporary designs. While a relatively minor problem was that the two-chip implementation of the GDP limited it to the speed of the motherboard's electrical wiring, a more serious issue was the lack of reasonable caches in the original implementation. The instruction set also used bit-aligned variable-length instructions (as opposed to the byte or word-aligned semi-fix formats used in the majority of computer designs), which made instruction decoding a little more complex than in most other designs. In addition, the BIU was designed to support fault-tolerant systems, and in doing so added considerable overhead to the bus, with up to 40% of the bus time held up in wait states.
However, post-project research suggested that the major problem was the Ada compiler developed for it, which used high-cost "general" instructions in every case, instead of high-performance simpler ones where it would have made sense to do so. For instance the iAPX 432 included a very expensive inter-module procedure call instruction, which the compiler used for all calls, despite the existence of much faster branch and link instructions. Another very slow call was enter_environment, which set up the memory protection. The compiler ran this for every single variable in the system, even though the vast majority were running inside an existing environment and did not have to be checked. To make matters worse, data passed to and from procedures was always passed by value rather than by reference: in many cases requiring huge memory copies.
An outcome of the failure of the 432 was that microprocessor designers concluded that object support in the chip leads to a complex design that will invariably run slowly, and the 432 was often cited as a counter-example by proponents of RISC designs. However it is held by some that the OO support was not the primary problem with the 432 and that the implementation shortcomings (especially in the compiler) mentioned above would have made any CPU design slow. Since the iAPX 432 there has been only one other attempt at a similar design, the Rekursiv processor, although the INMOS Transputer's process support was similar — and very fast.
Intel had spent considerable time, money and mindshare on the 432, had a skilled team devoted to it, and were unwilling to abandon it entirely after its failure in the marketplace. A new architect—Glenford Myers—was brought in to produce an entirely new architecture and implementation for the core processor, which would be built in a joint Intel/Siemens project (later BiiN), resulting in the i960-series processors. The i960 RISC subset became popular for a time in the embedded processor market, but the high-end 960MC and the tagged-memory 960MX were marketed only for military applications.
The iAPX 432 has hardware and microcode support for object-oriented programming and capability-based addressing. The system uses segmented memory, with up to 224 segments of up to 64 kB each, providing a total virtual address space of 240 bytes. The physical address space is 224 bytes (16 MB).
Programs are not able to reference data or instructions by address; instead they must specify a segment and an offset within the segment. Segments are referenced by Access Descriptors (ADs), which provide an index into the system object table and a set of rights (capabilities) governing accesses to that segment. Segments may be "access segments", which can only contain Access Descriptors, or "data segments" which cannot contain ADs. The hardware and microcode rigidly enforce the distinction between data and access segments, and will not allow software to treat data as access descriptors, or vice versa.
System-defined objects consist of either a single access segment, or an access segment and a data segment. System-defined segments contain data or access descriptors for system-defined data at designated offsets, though the operating system or user software may extend these with additional data. Each system object has a type field which is checked by microcode, such that a Port Object cannot be used where a Carrier Object is needed. User program can define new object types which will get the full benefit of the hardware type checking, through the use of Type Control Objects (TCO).
In Release 1 of the iAPX 432 architecture, a system-defined object typically consisted of an access segment, and optionally (depending on the object type) a data segment specified by an access descriptor at a fixed offset within the access segment.
By Release 3 of the architecture, in order to improve performance, access segments and data segments were combined into single segments of up to 128 kB, split into an access part and a data part of 0–64 kB each. This reduced the number of object table lookups dramatically, and doubled the maximum virtual address space.
Software running on the 432 does not need to explicitly deallocate objects that are no longer needed, and in fact no method is provided to do so. Instead, the microcode implements part of the marking portion of Edsger Dijkstra's on-the-fly parallel garbage collection algorithm (a mark-sweep style collector). The entries in the system object table contain the bits used to mark each object as being white, black, or grey as needed by the collector.
The iMAX-432 operating system includes the software portion of the garbage collector.
The iAPX 432 microcode implements multitasking, using objects in memory to represent the processor, processes, communication ports, and dispatching ports. Each processor is associated with a dispatching port, and when it is idle will attempt to dispatch a process from that dispatching port. When the process blocks or its time quantum expires, the processor re-enqueues that process at its dispatching port, then dispatches a new process from the dispatching port.
Interprocess communication is supported through the use of communication ports. A communication port is essentially a FIFO that can enqueue either messages waiting to be received by a process, or processes waiting to receive a message (but never both). A program can use the Send, Receive, Conditional Send, Conditional Receive, Surrogate Send, or Surrogate Receive instructions to communicate with other processes by sending messages to or receiving messages from communication ports. If there is no message enqueued at a communication port, a normal Receive instruction on that port will block the current process until a message is available. Similarly, a normal Send instruction will block the current process if the port is full. The Conditional Send and Conditional Receive instructions do not block, instead returning a Boolean result indicating whether the operation succeeded. The Surrogate Send and Surrogate Receive instructions provide a Carrier object that can block in place of the process.
One of the elegant aspects of the iAPX 432 architecture is that a dispatching port is actually just a communication port whose messages are process objects, thus unifying the operation of process dispatching and interprocess communication and simplifying the underlying implementation.
The iAPX 432 has hardware support for multiprocessing, using up to 64 processors (combination of GDPs and IPs). Usually, all GDPs share a common workload by using a single system-wide dispatching port, though it is possible to partition the workload by assigning some processors to different dispatching ports. With suitably designed hardware, processors can be added to or removed from the system on the fly.
From the outset, the iAPX 432 included support for fault tolerance. All of the 432's chips could be configured in pairs for Functional Redundancy Checking (FRC), in which one component, the master, operated normally, and a second, the checker, carried out the same internal operations in parallel and verified its results against those of the master.
FRC provides for failure detection, but full fault tolerance requires a recovery mechanism. Systems based on the Interconnect Architecture supported automatic failure recovery by combining pairs of FRC modules for Quad Modular Redundancy (QMR). In a QMR configuration, at any given time one FRC module is a primary and the other is a shadow. The two modules operate in lockstep, but the roles alternate to detect latent faults. The shadow module does not drive the bus. If a fault is detected in either FRC module, that module is disabled while the nonfaulted module can continue operation. The software is notified, and can choose to let the system continue operating (without fault tolerance for that module), pair the module with a spare, or take the module offline (shifting its workload to other processors in the system for graceful performance degradation).
The 43203 Interface Processor (IP) allows a more conventional microprocessor to be interfaced as an Attached Processor (AP) to an iAPX 432 system. The AP acts as an intelligent I/O controller. The IP allows the AP to access objects in the iAPX 432 memory through the use of memory-mapped windows, but enforces the access rights applicable to the objects.
The IP provides five memory windows. Four are used to map objects for I/O operations; the fifth is the control window and is used by the AP to perform control operations such as requesting changes to the mapping of the other windows.
The IP also offers a special "physical" mode in which the AP has unrestricted access to the entire iAPX 432 address space. Physical mode is intended to be used only for system startup and debugger support.
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